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Vishwakarma - Papers

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  1. N. Venkateswaran et al, "SCOC IP cores for Custom Built Supercomputing nodes", presented at the Annual Symposium on VLSI 2012, ISVLSI - 12 at University of Massachusetts Amherst
  2. N. Venkateswaran et al, "Compilation Acceleration on Silicon"", presented at the Annual Symposium on VLSI 2012, ISVLSI - 12 at University of Massachusetts Amherst
  3. N. Venkateswaran et al, "WIMAC - A Novel Many core simulator for very large clusters running multiple applications", demonstrated at the International Supercomputing Conference (ISC 2012), Hamburg Germany
  4. N. Venkateswaran et al, "Custom Built Heterogeneous Multi-core Architectures (CUBEMACH): Breaking the conventions", presented at the Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on Parallel and Distributed Computing
  5. N. Venkateswaran et al, "Towards Modeling and Integrated Design Automation of Supercomputing Clusters (MIDAS)", presented at the 24th International Supercomputing Conference ISC 09,Rome, Italy
  6. N.Venkateswaran et al., “Towards Node Architecture Designs for Realizing High Productivity Supercomputers”, presented at the pre-conference of 23rd International supercomputing conference 2008 (ISC 08) held at Dresden, Germany.
  7. N. Venkateswaran et al., “On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system,” in , 2008, 1-8, doi:10.1109/IPDPS.2008.4536347.
  8.  N.Venkateswaran, et al, "The MIP Project: Evolution of a Novel Supercomputer Architecture,MEmory access DEcoupled Architectures (MEDEA) Workshop, held in conjunction with Parallel Architectures and Compilation Techniques (PACT),2003
  9. N.Venkateswaran, et al, Memory In Processor: A Novel Design Paradigm for Supercomputing Architectures,ACM Computer Architecture News,2004
  10. N.Venkateswaran et al, Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance,International Parallel and Distributed Processing Systems (IPDPS),2005
  11. Venkateswaran N et al, High Performance Low Power Single Chip Reconfigurable Supercomputer for High-End Aerospace Applications ,8th International Conference on Military Aerospace Applications of Programmable Logic Devices, Washington DC,2005
  12. Venkateswaran N et al, Parallel Mapping of Simultaneous Multiple Applications (SMAPP) on a Multihost Hierarchical MIP SCOC Cluster,WARFT Workshop on Brain Modelling and Supercomputing, Chennai, India. March,2006
  13. N.Venkateswaran N et al, Memory Efficient Application Execution in MIP SCOC,WARFT Workshop,2006
 

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