Vishwakarma :

1. "Towards Modeling and Integrated Design Automation of Supercomputing Clusters (MIDAS)", presented at the 24th International Supercomputing Conference ISC 09, held at Rome, Italy
2. “Towards Node Architecture Designs for Realizing High Productivity Supercomputers”, presented at the pre-conference of 23rd International supercomputing conference 2008 (ISC 08) held at Dresden, Germany.
3. “On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system,” in , 2008, 1-8, doi:10.1109/IPDPS.2008.4536347.
4. "The MIP Project: Evolution of a Novel Supercomputer Architecture,MEmory access DEcoupled Architectures (MEDEA) Workshop, held in conjunction with Parallel Architectures and Compilation Techniques (PACT),2003
5. "Memory In Processor: A Novel Design Paradigm for Supercomputing Architectures",ACM Computer Architecture News,2004
6. "Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance",International Parallel and Distributed Processing Systems (IPDPS),2005
7. "High Performance Low Power Single Chip Reconfigurable Supercomputer for High-End Aerospace Applications", 8th International Conference on Military Aerospace Applications of Programmable Logic Devices, Washington DC,2005
8. "Parallel Mapping of Simultaneous Multiple Applications (SMAPP) on a Multihost Hierarchical MIP SCOC Cluster",WARFT Workshop on Brain Modelling and Supercomputing, Chennai, India. March,2006
9. "Memory Efficient Application Execution in MIP SCOC,WARFT Workshop,2006"

 Charaka :

1. “MMINi-DASS - Large-scale Brain Circuit Construction and Simulation for Interconnectivity Prediction, Frontiers in Neuroinformatics” (Neuroinformatics 08, Stockholm, Sweden)
2. “General Purpose Processor Architecture for Stochastic Biological Neuronal Assemblies (NAM)”, The 5th International Conference on Evolvable Systems: From Biology to Hardware,2003
3. "NAM For Massive Neuronal Assembly Modeling: Part-I, Processing Elements”,The 6th International Conference on Computational Intelligence and Natural Computing 2003.
4. "NAM For Massive Neuronal Assembly Modeling: Part-II The Array Architecture”, The 6th International Conference on Computational Intelligence and Natural Computing 2003
5. “Predicting the Morphology of Arbitrary Dendritic Trees through Simulated Annealing”, Engineering Intelligent Systems[EIS '04], Portugal, sponsored by International Computing Sciences Conference (ICSC) NAISO, and in co-operation with IEEE TC 2004.
6. "A Novel Perspective into the Neuronal Encoding along the Retinal Pathway Employing Time Frequency Transformation: Part-I - For Object,Brain Inspired Cognitive Systems,2004
7. "A Novel Perspective into the Neuronal Encoding along the Retinal Pathway Employing Time Frequency Transformation: Part-II - For Color",Brain Inspired Cognitive systems,2004
8. "Partitioned Parallel Processing Approach for Predicting Multi-Million Neuron Interconnectivity in the Brain Involving Soma-Axon-Dendrites-Synapse : A Simulation Model", Brain Inspired Cognitive Systems,2004
9. “Towards Predicting Multi-Million Neuron Interconnectivity involving Dendrites-Axon-Soma Synapse: A Simulation Model”, 7th International Conference on Computational Intelligence and Natural Computing in conjunction with 8th Joint Conference on Information Sciences (JCIS 2005) July 21 - 26, 2005, Salt Lake City, Utah,2005
10. “Simulation Model for predicting The Multi-Million Neuron Interconnectivity involving Dendrites-Axon-Soma-Synapse of the Brain Regions whose BOLD-fMRI is known and Evolution of a Neurophysiologically Inspired Supercomputing Architecture for Modeling the Respective Brain Regions”, Max Planck Institute of Medical Research Workshop, Data driven Modeling and Computational Neuroscience(DMCN) 2005, Heidelberg, Germany,2005
11. “On the Concept of Post Synaptic Current Tunneling Towards Modeling the Thought Process”, Towards a Science of Consciousness, Biennial Conference, Tucson, Arizona, March 8-11,2006
12. "DNA Based Evolutionary Approach for Microprocessor Design Automation", International Conference on Adaptive and Natural Computing Algorithms (ICANNGA 07, Poland),2006
13. "Microprocessor Design Automation: A DNA Based Evolutionary Approach", Brain Inspired Cognitive Systems (BICS 2006), Greece

 Naren :

1. "Analysis of Bit Transition Count for EDAC Encoded FSM", 9th IEEE International Online Testing Symposium, Kos Island, GREECE,2003
2. "Super Scalar Architecture For Billion Device Combinational And Sequential Circuit Test Design",39th IEEE AUTOTESTCON,2003
3. "An Encoding Scheme for Instruction, Data and Address in a Multi-GHz Processor for Concurrent crosstalk Fault Detection", 12th IEEE North Atlantic Test Workshop, Guerney's Inn at the Sea Montauk, New York, USA,2003
4. "On Complete Deterministic Testing Logic in BIST for High Availability systems", 4th Workshop on RTL and High Level Testing,2003
5. "Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design",The IEEE International Workshop on Electronic Design, Test and Applications (DELTA),2004
6. "Architecture Design in Finite Field (GFm) to achieve High Reliability in Multi GHz Processing", 13th IEEE North Atlantic Test Workshop (NATW).,2004
7. "Low power Fault Tolerant Digital Filter Design", North Atlantic Test Workshop,2004
8. "Analysis of Crosstalk Masking of Electromigration and On-Chip Tracking of Interconnect Aging",IEEE 14th North Atlantic Test Workshop May 11-13, 2005 The Inn at Essex Essex Junction, VT, USA,2005
9. "A Novel Integrated Approach for Low Power Testing and Fault Tolerance in Flash Type Analog to Digital Converters", The 12th IEEE North Atlantic Test Workshop,2003
10. "Frequency Domain Testing of General Purpose Processors at the Instruction Execution Level",2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA),2004
11. "Fault Tolerant Bus Architecture For Deep Submicron Based Processors",ACM SIGARCH news,2004
12. "Digital Model for Interconnect Analysis",23rd IEEE CAS, Norchip, Finland 2005

 Bhaskara :

1. "A 90nm Low Power Chip Design for High Performance DSP Applications",CoolChip VI Symposium, Japan, in conjecture with IEEE, April,2002
2. "Low Power Sparse Matrix Solvers for DSP Applications",2004
3. "High Performance Low Power Number System for DSP Processors",WARFT Workshop on Brain Modelling and Supercomputing, Chennai, India.
4. "Emerging Impact of DSM Technology on DFT and FFT Architectures",International Signal Processing Conference ISPC 2003, Dallas.,2002
5. "A Mixed number system based Low Power High Performance Arithmetic Architecture for DSP Applications",International Signal Processing Conference ISPC 2003, Dallas.,2002