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Custom Built Heterogeneous Multi-Core Architectures (CUBEMACH): Breaking the Conventions

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Conference : Heterogeneity in Computing Workshop held in conjunction with the International Parallel and Distributed Processing Symposium (IPDPS '10), Atlanta, Florida.

Title : Custom Built Heterogeneous Multi-Core Architectures (CUBEMACH): Breaking the Conventions

Authors : Nagarajan Venkateswaran*, Karthikeyan Palavedu Saravanan, Nachiappan Chidambaram Nachiappan, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundarajan

Abstract :
Increasing computational demand has stirred node architectures to move towards SuperComputer-On- Chips(SCOCs), where computational efficiency is emphasized over peak performance. Suitability of the architecture to a wider class of applications is becoming an pre-eminent design constraint for future HPC systems. This paper explores a novel design paradigm, the Custom Built Heterogeneous Multi-core Architectures (CUBEMACH) for realizing future generation node architectures. The CUBEMACH design flavoring a set of applications offers the possibility of increased resource utilization, which is exploited by running traces of multiple independent applications within a node without time or space sharing. A wide variety of complex Algorithm Level Functional units (ALFUs) besides scalars are used to meet high performance requirements of the grand challenge applications. To cater to the high communication bandwidth requirements across heterogeneous cores comprising these Algorithm Level Functional Units, a novel hierarchical communication backbone structure referred to as the On-Node- Network (ONNET) is used. The demand for high instruction issue rate due to the presence of a large number Algorithm Level Functional Units is catered by an Hardware based Compiler- On-Silicon(COS). The cost-effectiveness is achieved due to the the fact that the CUBEMACH design paradigm helps create an architecture for a single user for executing multiple independent applications without space time sharing.The cost effectiveness of implementing the CUBEMACH Design Paradigm is also achieved by developing SCOC IP cores for Higher Level Functional Us, Compiler-On-Silicon and On-Node-Network.

 

MMINi-DASS - Large-scale brain circuit construction and simulation for interconnectivity prediction

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Conference :

Neuroinformatics 2008. Stockholm, Sweden, September 07 - 09,  2008.

Title :

MMINi-DASS - Large-scale brain circuit construction and simulation for interconnectivity prediction

Authors :

Venkateswaran Nagarajan*, Karthik Srinivasan, Ashutosh Mohan, Vijay Daniel, Vijay R, Harish Chandran and Vignesh J

Abstract :

The MMINi-DASS framework[1,2] starts off with an arbitrary biological neural network which is statistically correct for a given brain region and a set of desired dynamics in the form of fMRI BOLD images. The constructed network is then simulated using computationally efficient and realistic models on a custom-made and event-driven simulator. Some models have been designed exclusively for the project while others are optimized implementations of existing models. The dynamics obtained from the simulation are then analyzed during run-time and compared with the desired dynamics by a Simulated Annealing Optimization engine. This then makes changes to the structure of the constructed network and invokes the simulation again, thus starting another loop. Evidently, the most interesting aspect of the MMINi-DASS project is the possibility of gaining structural, biophysical, biochemical and electrical knowledge from merely knowledge of the dynamics of a region initially.
Since the simulation is large-scale while also being detailed, the simulator is optimized for handling the large number of generated events efficiently. A Linux-based MPI (Message Passing Interface) cluster is setup. To handle the large amount of data generated, dedicated database architecture is used.
The whole system including the API (Application Programming Interface), simulator and analyzer are generic and are based on XML specifications. This eliminates the need to rebuild or reconfigure the system each time the logic for circuit building, models or analysis is modified. A change in the XML specifications automatically ripples throughout the system.
Among the most important problems for neuronal network simulations on a cluster are scalability, performance evaluation and improvement. The MMINi-DASS project uses a custom-made Performance Evaluator. This, while measuring the performance and resource utilization during run-time, also provides pointers to how performance scaling can be made linear with respect to problem size and architectural scaling within the current context and limitations. In the context of neuronal simulations, performance evaluation packages like HPL don’t provide accurate estimates. Thus, efforts are underway to use the BENSIM benchmarking package developed in-house for a realistic estimate of efficiency of both the implementation and the architecture.

 


 

 

Towards linking blood flow and neural activity : Petri net-based energetics model for neurons

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Conference :

Computational and systems neuroscience. Salt Lake City, UT, USA, February 26 - March 03, 2009.

Title :

Towards linking blood flow and neural activity : Petri net-based energetics model for neurons

Authors :

Venkateswaran Nagarajan and Ashutosh Mohan

Abstract :

The MMINi-DASS project at WARFT[1] is towards predicting an interconnectivity structure against a functional specification. fMRI is an important form of this specification and hence a computational method that links neuronal energetics with neuronal signalling is required. Our initial approach[1] was to model cerebral blood flow and link it with neuronal activity by conventional methods.Currently the main approach is to measure fMRI response and neuronal dynamics to arrive at a relationship between the two[2,3]. The authors believe that while such experimental methods are most valuable, a computational approach to solve this problem is a pressing need. Thus, we propose a Petri Net-based Energetics model for single-neurons in which both signaling and metabolism are considered. This is in contrast to current models which consider only signalling. The importance of metabolism is largely overlooked. A robust computational model to study both signaling and metabolism in a unified manner is required.

Petri nets consist of places(states), transitions and arcs connecting a place and a transition. Thus, it is a natural model to represent the complex chemical reactions of the neuron that characterize its energetics. Glycolysis, Kreb's cycle, the electron transport system and distribution of ATP to various cellular and signaling processes are modeled as a stochastic petri nets with tokens. Specifying all probabilistic state transitions is difficult due to a lack of experimental data. Thus, an optimization technique is used to fix up various transition values within their biologically realistic limits. For effective optimization when the number of parameters are large, a methodology based on Simulated Annealing and Game Theory has been developed at WARFT. This single-neuron model can then be used to perform fault simulation or study effects of various specific metabolic processes on neuronal signalling. While drawing significantly from experimental data for computational research, it will also drive experimental research.

This approach essentially provides only a framework using which we can rigorously approach problems relating to the link between blood flow and neural dynamics. Current work at WARFT is towards developing energetics-based soma and synapse models, fixing up petri-net transition probabilities using available data[4] and verifying their biological realism

Interconnectivity prediction against a functional specification like fMRI, electrophysiological recordings etc is a first of its kind effort undertaken at WARFT. To accomplish this, a novel approach of energetics-based neuron models is required. This requires a global effort and significant synergy between computational and experimental research.

 

On the Concept of Simultaneous Execution of Multiple Applications on Hierarchically Based Cluster and the Silicon Operating System

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Conference :

Large Scale Parallel Processing Workshop held in conjunction with the International Parallel and Distributed Processing Symposium (IPDPS '08)

Title :

On the Concept of Simultaneous Execution of Multiple Applications on Hierarchically Based Cluster and the Silicon Operating System

Authors :

N.Venkateswaran§, Vinoth Krishnan Elangovan♭, Karthik Ganesan♭, TP Ramnath Sai Sagar†, Sriram Aananthakrishanan†, Shreyas Ramalingam†, Shyamsundar Gopalakrishnan♭, Madhavan Manivannan♭, Deepak Srinivasan♭, Viswanath Krishnamurthy♭, Karthik Chandrasekar♭, Vishwanath Venkatesan♭, Balaji Subramaniam†, Vidya Sangkar L†, Aravind Vasudevan†, Shrikanth Ganapathy†, Sriram Murali†, Murali Thyagarajan†

Abstract :

In this paper we present a novel cluster paradigm and silicon operating system. Our approach in developing the competent cluster design revolves around an execution model to aid the execution of multiple independent applications simultaneously on the cluster, leading to cost sharing across applications. The execution model should envisage simultaneous execution of multiple applications (running traces of multiple independent applications in the same node at an instant, without time sharing) and on all the partitions(nodes) of a single cluster, without sacrificing the performance of individual application, unlike in the current cluster models. Performance scalability is achieved as we increase the number of nodes, the problem size of the individual independent applications, due to non-dependency across applications and hence increase in the number of non-dependent operations( as the problem sizes of the applications get increased) and this leads to better utilization of the unused resources within the node. This execution model is very much dependent on the node architecture for performance scalability. This would be a major initiative towards achieving performance Cost-Effective Supercomputing.

 

Towards Node Architecture Designs for Realizing High Productivity Supercomputers

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Conference :

23rd International Supercomputing Conference, ISC '08

Title :

Towards Node Architecture Designs for Realizing High Productivity Supercomputers

Authors :

V. Nagarajan*, K.Chandrasekar†§, S.Gopalakrishnan†¶, M.Manivannan †§, D.Srinivasan†k, V.Venkatesan†**, V.K.Elangovan†§, R.Sai Sagar†††, S.Murali‡, S.Ganapathy‡, A.Vasudevan‡, R.Mukundarajan‡, B.Subramaniam‡, V.Lakshmivenkatraman‡, S.Aananthakrishnan‡, S.Ramalingam‡, A.Mohan ‡, N.Nachiappan‡

*Founder Director, Waran Research Foundation, India,
†Former WARFT Research Trainee
‡WARFT Research Trainee, 2007-2009
§Delft University of Technology, Netherlands
¶Stanford University, USA
kUniversity of South Florida, USA
**University of Houston, USA
††EPFL, Switzerland

Abstract :

To meet the increasing requirements of computation intensive applications, many fundamentally divergent architectural approaches such as the TRIPS, Cascade and Cell BE have spurred. Although such approaches provide good performance, their role in achieving the goals of High Productivity Computing Systems remains unclear. In an attempt to address the productivity issue, we propose a novel homogeneously structured heterogeneous multi functional core architecture design and an execution model, which provides promising figures in terms of cost-efficiency without compromising on the requirements of the ever performance hungry applications. Such node architecture is capable of executing large number of Simultaneous Multiple AlGorithms, leading to performance scalable, cost effective and high productivity supercomputing. We present the design, which is based on Memory In Processor paradigm and discuss the related architectural aspects (ISA, Compiler, On Chip Network etc).We also explore the design space based on the proposed model, using a simulator that is being developed to analyze the system level parameters, which dictate the performance of such a node architecture.

 

 
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Bytes!

This year's conference on Brain Modeling and Supercomputing will be conducted on July 16th, 17th and 18th.