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SCOC IP cores for Custom Built Supercomputing Nodes presented at ISVLSI 12 by Rajagopal Hariharan

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Conference : Annual Symposium on VLSI 2012, ISVLSI - 12 at University of Massachusetts Amherst


Title : SCOC IP cores for Custom Built Supercomputing Nodes

Authors : Venkateswaran Nagarajan, Rajagopal Hariharan, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Bharanidharan Vasudevan, Nachiappan Chidambaram Nachiappan, Karthikeyan Palavedu Saravanan, Aswin Sridharan, Vigneshwaran Sankaran, Vignesh Adhinarayanan, V.S.Vignesh and Ravindhiran Mukundrajan

Abstract :
A high performance and low power node architecture becomes crucial in the design of future generation supercomputers. In this paper, we present a generic set of cells for designing complex functional units that are capable of executing an algorithm of reasonable size. They are called Algorithm Level Functional Units (ALFUs) and a suitable VLSI design paradigm for them is proposed in this paper. We provide a comparative analysis of many core processors based on ALFUs against ALUs to show the reduced generation of control signals and lesser number of memory accesses, instruction fetches along with increased cache hit rates, resulting in better performance and power consumption. ALFUs have led to the inception of the Super Computer On Chip (SCOC) IP core paradigm for designing high performance and low power supercomputing clusters. The proposed SCOC IP cores are compared with the existing IP cores used in supercomputing clusters to bring out the improved features of the former.

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Compilation Accelerator on Silicon presented at ISVLSI 12 by Rajagopal Hariharan

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Conference : Annual Symposium on VLSI 2012, ISVLSI - 12 at University of Massachusetts Amherst

Title : Compilation Accelerator on Silicon

Authors :   Venkateswaran Nagarajan, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Rajagopal Hariharan, Bharanidharan Vasudevan, Nachiappan Chidambaram Nachiappan, Karthikeyan Palavedu Saravanan, Aswin Sridharan, Vigneshwaran Sankaran, Vignesh Adhinarayanan, V.S.Vignesh and Ravindhiran Mukundrajan

Abstract :

Current day processors utilize a complex and finely tuned system software to map applications across their cores and extract optimal performance. However with increasing core counts and the rise of heterogeneity among cores, tremendous tress will be exerted on the software stack leading to bottlenecks and under utilization of resources. We propose an architecture or a Compilation Accelerator on Silicon (CAS) coupled with a hardware instruction scheduler to tackle the complexity involved in analyzing dependencies among instructions dynamically, accelerate machine code generation and obtain optimum resource utilization across the cores by effective and efficient scheduling. The CAS is realized as a two-level hierarchical subsystem employing the Primary Compiler on Silicon (PCOS) and Secondary compiler on Silicon (SCOS) with the hardware instruction scheduler as an integral part of it. A comparative analysis with the conventional GCC compiler is presented for a real world brain modeling application and higher instruction generation rates along with improved scheduling efficiency is observed resulting in a corresponding increase in resource utilization.

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Morphology and Synaptic Characteristics Based Prediction of Visual Cortex Spike Properties for Different Functions presented at INCF 2012 by Vignesh SR and Ramprakash

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Conference : International Neuroinformatics Coordinating Facility (INCF), 2012

Title : Morphology and Synaptic Characteristics Based Prediction of Visual Cortex Spike Properties for Different Functions

Authors : Venkateswaran Nagarajan, Vignesh Saptarishi Ramesh, Dinesh Kannan Kabaleeswaran, Ramprakash Srinivasan, Vishal Raghu, Sharan Srinivas Jagathrakshakan,Sharath Navalpakkam Krishnan, Thiagarajan TS


Abstract :
The need to improve understanding of cortical organization dependent functioning of visualcortex actuated this initiative where we are trying to establish a relationship across functions defined by visualcortex(edge detection,segment analysis,orientation specificity,motion processing)& morphological properties including dendritic arborization,soma geometry & synapse characteristics of regions involved in discharging these functions.Computer architectures like VonNeumann or Harvard model have separate memory for instructions & data & standalone functional units unlike the brain where the synapse with plasticity in addition to laying a foundation for long term & short term memory also plays a major role in functional aspects.Existing synapse models have accounted for synapse characteristics like plasticity only for single synapse whereas plasticity study for network of synapses & neurons has been minimal.We define RegionalSynapticPlasticity(RSP) for network of neurons which is essential to link synapse characteristics to functions performed by specific network through spatiotemporal spike distribution.Linking morphology & spike activity for single neuron is brought about by modeling postsynaptic current as stochastic function of concentration of neurotransmitter,state of receptors,membrane reversal potential,among structural parameters including dendritic spanning & synaptic geometry.Further improvements can be done by capturing spike activity of network as function of intracellular parameters1.This single neuron model is extended to network of neurons using ChapmanKolmogorov equation to relate independent probability densities which under appropriate assumptions is reduced to PDE thereby establishing link between RSP,morphology & spike activity of the network.The relationship is established independently for each region of the visualcortex by varying parameters for the network from empirical data.With this relationship an ongoing investigation is undertaken to link morphology & spike activity of separate regions of visualcortex to the functions they are responsible for, which can help in the fundamental understanding of visualcortex. We believe that this understanding of synapse & morphology can also contribute in replacing current VonNeumann & Harvard computer models with more efficient brain-inspired ones.

 

 

Custom Built Heterogeneous Multi-Core Architectures (CUBEMACH): Breaking the Conventions presented at HCW workshop by Balaji Subramaniam

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Conference : Heterogeneity in Computing Workshop held in conjunction with the International Parallel and Distributed Processing Symposium (IPDPS '10), Atlanta, Florida.

Title : Custom Built Heterogeneous Multi-Core Architectures (CUBEMACH): Breaking the Conventions

Authors : Nagarajan Venkateswaran*, Karthikeyan Palavedu Saravanan, Nachiappan Chidambaram Nachiappan, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundarajan

Abstract :
Increasing computational demand has stirred node architectures to move towards SuperComputer-On- Chips(SCOCs), where computational efficiency is emphasized over peak performance. Suitability of the architecture to a wider class of applications is becoming an pre-eminent design constraint for future HPC systems. This paper explores a novel design paradigm, the Custom Built Heterogeneous Multi-core Architectures (CUBEMACH) for realizing future generation node architectures. The CUBEMACH design flavoring a set of applications offers the possibility of increased resource utilization, which is exploited by running traces of multiple independent applications within a node without time or space sharing. A wide variety of complex Algorithm Level Functional units (ALFUs) besides scalars are used to meet high performance requirements of the grand challenge applications. To cater to the high communication bandwidth requirements across heterogeneous cores comprising these Algorithm Level Functional Units, a novel hierarchical communication backbone structure referred to as the On-Node- Network (ONNET) is used. The demand for high instruction issue rate due to the presence of a large number Algorithm Level Functional Units is catered by an Hardware based Compiler- On-Silicon(COS). The cost-effectiveness is achieved due to the the fact that the CUBEMACH design paradigm helps create an architecture for a single user for executing multiple independent applications without space time sharing.The cost effectiveness of implementing the CUBEMACH Design Paradigm is also achieved by developing SCOC IP cores for Higher Level Functional Us, Compiler-On-Silicon and On-Node-Network.

 

 

Energetics based spike generation of a single neuron : simulation results and analysis

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Journal : Frontiers in Neuroenergetics, 2012

Title : Energetics based spike generation of a single neuron: simula-tion results and analysis

Authors : Nagarajan Venkateswaran, Sudarshan Sekhar, Thiagarajan Thirupatchur Sanjayasarathy, Sharath Navalpakkam Krishnan, Dinesh Kannan Kabaleeswaran, Subbu Ramanathan, Narendran Narayanasamy, Sharan Srinivas Jagathrakshakan and S. R. Vignesh


Abstract :

The onset of great advances in computational capability, coupled with the moral dilemma often faced with traditional brain research has prompted a non-invasive approach towards understanding the brain. Significant effort at WARFT has been routed towards capturing the spike activity of the neuron as a function of its intracellular parameters (Venkateswaran, et al). Our voltage spike - energetics model assumes a lumped nature of the mitochondria and other intracellular organelles, and doesn’t consider the individual contributions of the mitochondrial cloud inside the soma and the spatial communication across the intracellular organelles. It localizes the energy budget of the neuron to a single global mitochondrion and does not consider mechanisms such as ATP communication and transportation across the organelles such as nucleus, ER, peroxisomes ,and the golgi apparatus with a commensurate level of biological accuracy. In this poster, we propose a novel distributed model of intracellular organelles, which analyzes the energetics in a three-dimensional environment, with emphasis laid on the spatial distribution of various organelles and the associated inter-dependencies across them.

The Three-Dimensional framework for the voltage-spike energetics model is set up by dividing the total mitochondria (and hence the energy budget ) in a neuron among the various energy consuming entities (organelles). The plane containing these organelles is divided into infinitesimally small segments on which the mitochondria are localised. Stochastic equations are developed to model the transition of mitochondria across various “states” which represent its physical coordinates along the segment. The solution of this system of equations gives the probability distribution of mitochondria which is used to model mechanisms such as ATP consumption, restoration of ionic gradient and neurotransmitter packing. The developed energetics model for the organelles is distributed as hyper-nodes in a graph with the inter-dependencies optimised to simulate a distributed neuron. This has prompted the development of a generic framework which can analyse the commonalities present in biochemical signalling mechanisms such as the phosphorylation-dephosphrylation switch, diffusion and docking of vesicles in a simulation environment. Parallel research at WARFT is aimed at establishing a relationship across functions defined by the various regions of the visual cortex and morphological properties of the neurons in a specific layer. The morphological model provides the crucial link between functionality and energetics in the central nervous system and this highly integrated morphology-functionality-enrgetics model will lead to a more comprehensive understanding of the visual cortex .

 

 
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